1. Technical Field
This disclosure relates to integrated circuits, and more particularly, to the control of a clock signal to circuitry implemented on an integrated circuit.
2. Description of the Related Art
Clock-gating is a power saving technique that is employed in a wide variety of integrated circuits (ICs). In an IC operable to perform clock-gating, extra hardware in the form of clock-gating logic is added to various points of a clock tree that is used to distribute a clock signal. A point of a clock tree used to distribute the clock signal directly to circuitry (e.g., flop circuits) may be referred to as a “leaf” node. Accordingly, clock-gating logic may be placed at the leaf node. The clock-gating logic of each leaf node may be coupled to receive an enable signal that, when asserted, enables the clock signal to be provided to the clock circuitry associated with that leaf node. The enable signal may be de-asserted to inhibit the clock signal from being provided to circuitry coupled to a corresponding leaf node when that circuitry is idle, thereby saving power.
Circuitry for implementing clock-gating may include logic to detect when various circuits are idle. Idle times may be defined as a specified amount of time that a given circuit or block of logic is inactive (e.g., is not processing data in some manner). One or more logic blocks may be implemented to monitor those functional blocks for which clock-gating is supported. If a functional block has been idle for a sufficient amount of time, a corresponding clock enable signal may be asserted. If another unit attempts to communicate with a clock-gated functional block while it is idle, the clock enable signal may be de-asserted, and other actions may be performed to re-start the clock signal to the previously idled functional block.